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可信计算机结构与组织（英文版）

暂无简介
作者：
Shuangbao (Paul) Wang (王双保)
定价：
149.00元
出版时间：
2021-08-18
ISBN：
978-7-04-055893-7
物料号：
55893-00
读者对象：
学术著作
一级分类：
自然科学
二级分类：
计算机科学与工程
三级分类：
计算理论与算法
重点项目：
暂无
版面字数：
600.000千字
开本：
特殊
全书页数：
暂无
装帧形式：
精装
  • 前辅文
  • Chapter 1 Introduction to Computer Architecture andOrganization
    • 1.1 History of Computer Systems
      • 1.1.1 Timeline of Computer History
      • 1.1.2 Timeline of Internet History
      • 1.1.3 Timeline of Computer Security History
    • 1.2 John von Neumann Computer Architecture
    • 1.3 Memory and Storage
    • 1.4 Input, Output and Network Interface
    • 1.5 Single CPU and Multiple CPU Systems
    • 1.6 Overview of Computer Security
      • 1.6.1 Confidentiality
      • 1.6.2 Integrity
      • 1.6.3 Availability
      • 1.6.4 Threats
      • 1.6.5 Firewalls
      • 1.6.6 Hacking and Attacks
    • 1.7 Security Problems in Neumann Architecture
    • 1.8 Trusted Computing Base
    • 1.9 Mobile Architecture
    • 1.10 IoT Architecture
    • 1.11 Cloud Architecture
    • 1.12 Summary
    • Exercises
    • Projects
    • References
  • Chapter 2 From Logic Circuit to Quantum Circuit
    • 2.1 Concept of Logic Unit
    • 2.2 Logic Functions and Truth Tables
    • 2.3 Boolean Algebra
    • 2.4 Logic Circuit Design Process
    • 2.5 Gates and Flip-f lops
    • 2.6 Hardware Security
    • 2.7 FPGA and VLSI
    • 2.8 RFID and NFC
      • 2.8.1 A RIFD Student Attendance System
      • 2.8.2 Near Field Communication
    • 2.9 Trusted Platform Module
    • 2.10 Physical Unclonable Function
    • 2.11 Quantum Circuit
    • 2.12 Summary
    • Exercises
    • Projects
    • References
  • Chapter 3 Computer Memory and Storage
    • 3.1 A One-Bit Memory Circuit
    • 3.2 Memory Hierarchy
    • 3.3 Cache Memory
    • 3.4 Virtual Memory
      • 3.4.1 Paged Virtual Memory_
      • 3.4.2 Segmented Virtual Memory_
    • 3.5 Non-Volatile Memory
      • 3.5.1 The Concept of Computer Memory Before 1985
      • 3.5.2 The Wide Use of Flash Memory Since the 21stCentury
    • 3.6 External Memory
      • 3.6.1 Hard Disk Drives and Solid-State Drives
      • 3.6.2 Tertiary Storage and Off-Line Storage_
      • 3.6.3 Serial Advanced Technology Attachment
      • 3.6.4 Small Computer System Interface
      • 3.6.5 Serial Attached SCSI
    • 3.7 Networked Memory
      • 3.7.1 Network-Attached Storage_
      • 3.7.2 Storage Area Network_
    • 3.8 Cloud Storage
      • 3.8.1 Amazon S3
      • 3.8.2 OneDrive, Dropbox, and iCloud
    • 3.9 Memory Access Security
    • 3.10 Summary
    • Exercises
    • Projects
    • References
  • Chapter 4 Bus and Interconnection
    • 4.1 System Bus
      • 4.1.1 Address Bus
      • 4.1.2 Data Bus
      • 4.1.3 Control Bus
    • 4.2 Parallel Bus and Serial Bus
      • 4.2.1 Parallel Buses and Parallel Communication
      • 4.2.2 Serial Bus and Serial Communication
      • 4.2.3 Ethernet
      • 4.2.4 MIDI_
    • 4.3 Synchronous Bus and Asynchronous Bus
    • 4.4 Single Bus and Multiple Buses
    • 4.5 Interconnection Buses
    • 4.6 Font-Side Bus and Northbridge
    • 4.7 Internal Bus
    • 4.8 Low Pin Count and Southbridge
    • 4.9 Security Considerations for Computer Buses
    • 4.10 A Dual-Bus Interface Design
      • 4.10.1 Dual-Channel Architecture_
      • 4.10.2 Triple-Channel Architecture_
      • 4.10.3 A Dual-Bus Memory Interface
    • 4.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 5 I/O and Network Interface
    • 5.1 Direct Memory Access
    • 5.2 Interrupts
    • 5.3 Programmed I/O
    • 5.4 USB and IEEE 1394
      • 5.4.1 USB Advantages
      • 5.4.2 USB Architecture
      • 5.4.3 USB Version History
      • 5.4.4 USB Design and Architecture_
      • 5.4.5 USB Mass Storage
      • 5.4.6 USB Interface Connectors
      • 5.4.7 USB Connector Types
      • 5.4.8 USB Power and Charging
      • 5.4.9 IEEE 1394
      • 5.4.10 USB 3.0
    • 5.5 Network Interface Card
      • 5.5.1 Basic NIC Architecture
      • 5.5.2 Data Transmission
    • 5.6 Keyboard, Video and Mouse Interfaces
      • 5.6.1 Keyboards
      • 5.6.2 Video Graphics Cards
      • 5.6.3 Mouses
    • 5.7 Virtual I/O
    • 5.8 Software Defined Networking
    • 5.9 3D I/O Devices
      • 5.9.1 3D Scanners
      • 5.9.2 3D Printers
      • 5.9.3 Autonomous Eyes
    • 5.10 Input / Output Security
      • 5.10.1 Disable Certain Key Combinations
      • 5.10.2 Anti-Glare Displays
      • 5.10.3 Adding Password to Printers
      • 5.10.4 Bootable USB Ports
      • 5.10.5 Encrypting Hard Drives
    • 5.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 6 Central Processing Unit
    • 6.1 The Instruction Set
      • 6.1.1 Instruction Set Architecture
      • 6.1.2 Instruction Classifications
      • 6.1.3 Logic Instructions
      • 6.1.4 Arithmetic Instructions
      • 6.1.5 Intel 64/32 Instructions_
    • 6.2 Registers
      • 6.2.1 General-Purpose Registers
      • 6.2.2 Segment Registers
      • 6.2.3 EFLAGS Register
    • 6.3 The Program Counter and Flow Control
      • 6.3.1 Intel Instruction Pointer_
      • 6.3.2 Interrupt and Exception_
    • 6.4 RISC Processors
      • 6.4.1 History
      • 6.4.2 Architecture and Programming
      • 6.4.3 Performance
      • 6.4.4 Advantages and Disadvantages
      • 6.4.5 Applications
    • 6.5 Pipelining
      • 6.5.1 Different Types of Pipelines
      • 6.5.2 Pipeline Performance Analysis
      • 6.5.3 Data Hazard
    • 6.6 Virtual CPU
      • 6.6.1 Virtual Processor
      • 6.6.2 Intel VT_
      • 6.6.3 Raspberry Pi Emulation with QEMU
    • 6.7 Mobile Processors
    • 6.8 GPU
    • 6.9 TPU
    • 6.10 CPU Security
    • 6.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 7 Advanced Computer Architecture
    • 7.1 Multiprocessors
      • 7.1.1 Multiprocessing
      • 7.1.2 Cache
      • 7.1.3 Hyper-Threading
      • 7.1.4 Symmetric Multiprocessing
      • 7.1.5 Multiprocessing Operating Systems
      • 7.1.6 The Future of Multiprocessing
    • 7.2 Parallel Processing
      • 7.2.1 History of Parallel Processing
      • 7.2.2 Flynn’s Taxonomy
      • 7.2.3 Bit-Level Parallelism
      • 7.2.4 Instruction-Level Parallelism
      • 7.2.5 Data-Level Parallelism
      • 7.2.6 Task-Level Parallelism
      • 7.2.7 Memory in Parallel Processing
      • 7.2.8 Specialized Parallel Computers
      • 7.2.9 The Future of Parallel Processing
    • 7.3 Grid and Distributed Computing
      • 7.3.1 Characteristics of Grid Computing
      • 7.3.2 The Advantages and Disadvantages of Grid Computing
      • 7.3.3 Distributed Computing
      • 7.3.4 Distributed Systems
      • 7.3.5 Parallel and Distributed Computing
      • 7.3.6 Distributed Computing Architectures
    • 7.4 Ubiquitous and Internet Computing
      • 7.4.1 Ubiquitous Computing Development
      • 7.4.2 Basic Forms of Ubiquitous Computing
      • 7.4.3 Augmented Reality
      • 7.4.4 Internet Computing Concept and Model
      • 7.4.5 Benefit of Internet Computing for Businesses
      • 7.4.6 Examples of Internet Computing
      • 7.4.7 Migrating to Internet Computing
    • 7.5 Virtualization
      • 7.5.1 Types of Virtualization
      • 7.5.2 History of Virtualization
      • 7.5.3 Virtualization Architecture
      • 7.5.4 Virtual Machine Monitor
      • 7.5.5 Examples of Virtual Machines
    • 7.6 Cloud Computing Architecture
      • 7.6.1 Cloud Architecture
      • 7.6.2 Technical Aspects of Cloud Computing
      • 7.6.3 Security Aspects of Cloud Computing
      • 7.6.4 Ongoing and Future Elements in Cloud Computing
      • 7.6.5 Adoption of Cloud Computing Industry Drivers
    • 7.7 Mobile Computing Architecture
      • 7.7.1 Mobile Apps
      • 7.7.2 Android App Development
      • 7.7.3 Apple iOS App Development
      • 7.7.4 Mobile Computing in The Cloud
    • 7.8 Biocomputers
      • 7.8.1 Biochemical Computers
      • 7.8.2 Biomechanical Computers
      • 7.8.3 Bioelectronic Computers
    • 7.9 Quantum Computing: IBM Q
      • 7.9.1 Qubits
      • 7.9.2 Quantum Logic Gates
      • 7.9.3 Operations_
      • 7.9.4 Qiskit
    • 7.10 Architecture for AI Applications
    • 7.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 8 Assembly Language and Operating Systems
    • 8.1 Assembly Language Basics
      • 8.1.1 Numbering Systems
      • 8.1.2 The Binary Numbering System and Base Conversions
      • 8.1.3 The Hexadecimal Numbering System
      • 8.1.4 Signed and Unsigned Numbers
    • 8.2 Instructions
    • 8.3 Direct and Indirect Addressing
    • 8.4 Stack and Buffer Overflow
      • 8.4.1 Calling Procedures Using CALL and RET (return)
      • 8.4.2 Exploiting Stack Buffer Overflows
      • 8.4.3 Stack Protection
    • 8.5 FIFO and M/M/1 Problem
      • 8.5.1 FIFO Data Structure
      • 8.5.2 M/M/1 Model
    • 8.6 Kernel, Drivers and OS Security
      • 8.6.1 Kernel
      • 8.6.2 BIOS
      • 8.6.3 Boot Loader
      • 8.6.4 Device Drivers
    • 8.7 Windows, Linux and Mac OS
      • 8.7.1 Windows OS and Security
      • 8.7.2 Linux, Mac OS and Security
      • 8.7.3 Kali Linux
    • 8.8 Mobile OS
      • 8.8.1 iOS
      • 8.8.2 Android
    • 8.9 Network OS
    • 8.10 Software Reverse Engineering
      • 8.10.1 Debug Tools (IDA and Ghidra)
      • 8.10.2 Discovering APIs and DLLs
      • 8.10.3 Decompilation and Disassembly
    • 8.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 9 Communication, TCP/IP and Internet
    • 9.1 Data Communications
      • 9.1.1 Signal, Data and Channels
      • 9.1.2 Signal Encoding and Modulation
      • 9.1.3 Shannon Theorem
    • 9.2 TCP/IP Protocol
      • 9.2.1 Network Topology
      • 9.2.2 Transmission Control Protocol
      • 9.2.3 User Datagram Protocol
      • 9.2.4 Internet Protocol
    • 9.3 Network Switches
      • 9.3.1 Layer 1 Hubs
      • 9.3.2 Ethernet Switch
      • 9.3.3 Virtual Switches
    • 9.4 Routers
      • 9.4.1 History of Routers
      • 9.4.2 Architecture
      • 9.4.3 Internet Protocol Version 4
      • 9.4.4 Internet Protocol Version 6
      • 9.4.5 Open Shortest Path First
      • 9.4.6 Throughput and Delay
    • 9.5 Gateways
    • 9.6 Wireless Networks and Network Address Translation
      • 9.6.1 Wireless Networks
      • 9.6.2 Bluetooth
      • 9.6.3 Wireless Protocols
      • 9.6.4 WLAN Handshaking, War Driving and WLAN Security
      • 9.6.5 Security Measures to Reduce Wireless Attacks
      • 9.6.6 The Future of Wireless Network
      • 9.6.7 Network Address Translation
      • 9.6.8 Environmental and Health Concerns Using Cellular and Wireless Devices
    • 9.7 Mobile Networks
      • 9.7.1 Modern Wireless and Mobile Networks
      • 9.7.2 3GPP Initiatives
      • 9.7.3 Long-Time Evolution
      • 9.7.4 Mobile 5G
      • 9.7.5 Security and Privacy
    • 9.8 Network Security
      • 9.8.1 Introduction
      • 9.8.2 Firewall Architecture
      • 9.8.3 Constraint and Limitations of Firewall
      • 9.8.4 Enterprise Firewalls
      • 9.8.5 Intrusion Detection and Prevention
      • 9.8.6 Security Logs and Log Analysis
    • 9.9 IoT Architecture
      • 9.9.1 IoT Reference Model
      • 9.9.2 Paired Firewall Architecture
      • 9.9.3 Defense-in-Depth SCADA Architecture
      • 9.9.4 IoTCP–Trusted Computing Protocol for IoT
    • 9.10 VPN and VPC
    • 9.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 10 Cryptography and Architecture Security
    • 10.1 Zimmermann Telegram
    • 10.2 Substitution Cipher
      • 10.2.1 Simple Substitution Cipher
      • 10.2.2 Cryptologic Analysis of Substitution Cipher
    • 10.3 Symmetric Key Algorithms
      • 10.3.1 DES, 3DES and AES
      • 10.3.2 Key Generation and Management
    • 10.4 Public Key Encryption
      • 10.4.1 RSA
      • 10.4.2 Certificate Authority
      • 10.4.3 Secure Socket Layer
    • 10.5 Hash vs. Encryption
      • 10.5.1 Hash Functions
      • 10.5.2 HMAC
      • 10.5.3 Random Numbers
    • 10.6 Strong Encryptions
      • 10.6.1 Pretty Good Privacy
      • 10.6.2 Transport Layer Security
      • 10.6.3 Elliptic Curve Cryptography
    • 10.7 Authentication
      • 10.7.1 Access Control
      • 10.7.2 Username and Password
      • 10.7.3 Biometrics
      • 10.7.4 Multi-Factor Authentication
      • 10.7.5 Security Models
    • 10.8 Cryptographic Hardware_
      • 10.8.1 PCI Cryptographic Coprocessor
      • 10.8.2 AES-NI
    • 10.9 Privacy and Anonymity
      • 10.9.1 RSA Key Splitter
      • 10.9.2 Blockchain
      • 10.9.3 Cryptocurrency
      • 10.9.4 Smart Contracts
    • 10.10 Quantum Cryptography
      • 10.10.1 Cryptographic Key Distribution
      • 10.10.2 Shor’s Algorithm
      • 10.10.3 Quantum Error Correction
      • 10.10.4 Post Quantum Cryptography
    • 10.11 Summary
    • Exercises
    • Projects
    • References
  • Chapter 11 Design and Implementation: Modifying Neumann Architecture
    • 11.1 Data Security in Computer Systems
      • 11.1.1 Computer Security
      • 11.1.2 Data Security and Data Bleaches
      • 11.1.3 Researches in Architecture Security
    • 11.2 Single-Bus View of Neumann Architecture
      • 11.2.1 John von Neumann Computer Architecture
      • 11.2.2 Modified Neumann Computer Architecture
      • 11.2.3 Problems Exist in The Neumann Model
    • 11.3 A Dual-Bus Solution
    • 11.4 Bus Controller
      • 11.4.1 Working Mechanism of The Bus Controller
      • 11.4.2 Co-Processor Board
    • 11.5 Dual-Port Storage
    • 11.6 Micro-Operating System
    • 11.7 Putting Together
    • 11.8 Summary
    • Exercises
    • References

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