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Computer Architecture and Security



在当今的计算机和信息系统应用设计中，计算机和信息安全专业人员必须同时了解硬件和软件才能有效地部署安全解决方案。《信息安全系列：计算机体系结构与安 全（英文版）》从安全的角度对计算机和网络硬件、系统软件、信息和数据的概念进行全面的阐述，并为读者提供实现安全的计算机和信息系统的解决方案和工具； 此外，在计算机安全、信息集成设计与实践经验方面还介绍了现代计算机系统以及作者所拥有的一些专利技术，以使读者更好地掌握和应用计算机安全系统的知识。 《信息安全系列：计算机体系结构与安全（英文版）》可作为高等学校计算机、电子与通信以及信息安全学科高年级本科生和研究生教材，也可供相关专业研究人 员、安全专家以及工程师参考。

作者：
Shuangbao (Paul) Wang (王双保） Robert S. Ledley (罗伯特•莱德利) 著
定价：
69.00元
出版时间：
2012-11-30
ISBN：
978-7-04-034492-9
物料号：
34492-00
读者对象：
学术著作
一级分类：
自然科学
二级分类：
计算机科学与工程
三级分类：
计算理论与算法
重点项目：
暂无
版面字数：
490.000千字
开本：
16开
全书页数：
321页
装帧形式：
精装
  • 前辅文
  • 1 Introductiontocomputer Architecture and Security
    • 1.1 Historyofcomputer Systems
      • 1.1.1timelineo fcomputer History
      • 1.1.2timelineo f Internet History1
      • 1.1.3timeline ofcomputer Security History
    • 1.2 John von Neumanncomputer Architecture
    • 1.3 Memory and Stor age 3
    • 1.4 in put/Output and Network Inter face3
    • 1.5 SinglecPU and MultiplecPU Systems
    • 1.6 Overview ofcomputer Security
      • 1.6.1confidential ity
      • 1.6.2 integrity4
      • 1.6.3 Availabil ity
      • 1.6.4threat s
      • 1.6.5 Fi rewalls
      • 1.6.6 Hacking and Attacks
    • 1.7 Security Problems in Neumann Architecture
    • 1.8 Summary
    • Exerci ses
    • References
  • 2 Digitallogic Design
    • 2.1 conce ptoflogic Unit
    • 2.2 logic Functions andtruthtables
    • 2.3 Boolean Algebra
    • 2.4 logicci rcuitDes ign Process
    • 2.5 gat es and Flip-Fl ops
    • 2.6 HardwareSecur ity
    • 2.7 FPGA and VLSI
      • 2.7.1 Design of an FPGA Biometric Security System
      • 2.7.2 A RIFD Student Attendance System
    • 2.8 Summa ry
    • Exercises
    • References
  • 3 computer Memory and Storage
    • 3.1 A One Bit Memoryci rcuit
    • 3.2 Register, MAR, MDR and Main Memory
    • 3.3 cacheMemory
      • 3.4 Virtual Memory
      • 3.4.1 Paged Vi rtual Memory*
      • 3.4.2 Segmented Vi rtual Memory*
    • 3.5 Non-Vol atileMemory
    • 3.6 Ext ernal Memory
      • 3.6.1 Hard Disk Drives7
      • 3.6.2tertiary Storage and Off-Line Storage*
      • 3.6.3 Serial Advancedtechnology Attachment (SATA)
      • 3.6.4 Smallcomputer System Interface (SCSI)
      • 3.6.5 Serial Attached SCSI (SAS)
      • 3.6.6 Network-Attached Storage (NAS) *
      • 3.6.7 Storage Area Network (SAN) *
      • 3.6.8cloudstorage
    • 3.7 Memory Access Security 8
    • 3.8 Summa ry
    • Exercises
    • References
  • 4 Bus and Int erconnection
    • 4.1 System Bus
      • 4.1.1 Address Bus
      • 4.1.2 Dat a Bus
      • 4.1.3control Bus
      • 4.2 Parallel Bus and Ser ial Bus
      • 4.2.1 Parallel Buses and Parallelcommunication
      • 4.2.2 Serial Bus and Ser ialcommunication
    • 4.3 Synchronous Bus and Asynchronous Bus
    • 4.4 Single Bus and Multiple Buses
    • 4.5 Interconnection Buses
    • 4.6 Securityconsiderations forcomputer Buses
    • 4.7 A Dual-Bus Interface Design
      • 4.7.1 Dual-Channel Architecture*
      • 4.7.2triple-Channel Architecture*
      • 4.7.3 A Dual-Bus Memory Interface
    • 4.8 Summary
    • Exercises
    • References
  • 5 I/O and Network Interface
    • 5.1 Direct Memory Access
    • 5.2 Interrupt s
    • 5.3 Programmed I/O
    • 5.4 USB and IEEE 1394
      • 5.4.1 USB Advantages
      • 5.4.2 USB Architecture
      • 5.4.3 USB Version History
      • 5.4.4 USB Design and Architecture*
      • 5.4.5 USB Mass Storage
      • 5.4.6 USB Interfaceconnectors
      • 5.4.7 USBconnectortypes
      • 5.4.8 USB Power andcharging
      • 5.4.9 IEEE 1394
    • 5.5 Network Interfacecard
      • 5.5.1 Basic NIC Architecture
      • 5.5.2 Datatransmission
    • 5.6 Keyboard, Video and Mouse (KVM) Interfaces
      • 5.6.1 Keyboards
      • 5.6.2 Videographiccard
      • 5.6.3 Mouses
    • 5.7 Input/Output Security
      • 5.7.1 Disablecertain Keycombinations
      • 5.7.2 Anti-Glare Displays
      • 5.7.3 Adding Passwordto Printer
      • 5.7.4 Bootable USB Ports
      • 5.7.5 Encrypting Hard Drives
    • 5.8 Summary
    • Exercises
    • References
  • 6 central Processing Unit
    • 6.1 the Inst ruct ion Set
      • 6.1.1 Instructionclassifications
      • 6.1.2logic Instructions
      • 6.1.3 Arithmetic Instructions
      • 6.1.4 Intel 64/32 Instructions*
    • 6.2 Registers
      • 6.2.1general-Purpose Registers
      • 6.2.2 Segment Registers
      • 6.2.3 EFLAGS Register
    • 6.3 the Programcounter and Flowcontrol
      • 6.3.1 Intel Instruction Pointer*
      • 6.3.2 Interrupt and Exception*
    • 6.4 RISC Processors
      • 6.4.1 Hi story
      • 6.4.2 Architecture and Programming
      • 6.4.3 Performance
      • 6.4.4 Advantages and Disadvantages
      • 6.4.5 Applicat ions
    • 6.5 Pipel ining
      • 6.5.1 Differenttypes of Pipelines
      • 6.5.2 Pipeline Performance Analysis
      • 6.5.3 Data Hazard
    • 6.6 cPU Security
    • 6.7 VirtualcPU
    • 6.8 Summary
    • Exercises
    • References
  • 7 Advancedcomputer Architecture
    • 7.1 Multiprocessors
      • 7.1.1 Multiprocessing
      • 7.1.2cache
      • 7.1.3 Hyper-Threading
      • 7.1.4 Symmetric Multiprocessing
      • 7.1.5 Multiprocessing Operating Systems
      • 7.1.6 the Future of Multiprocessing
    • 7.2 Parallel Processing
      • 7.2.1 History of Parallel Processing
      • 7.2.2 Flynn'staxonomy
      • 7.2.3 Bit-Level Parallelism
      • 7.2.4 in struction-Level Par allelism
      • 7.2.5 Dat a-Level Parall elism
      • 7.2.6 task-Level Par allel ism
      • 7.2.7 Memory in Parallel Processing
      • 7.2.8 Specialized Parallelcomputers
      • 7.2.9 the Future of Parallel Processing
    • 7.3 Ubiquitouscomput ing
      • 7.3.1 Ubiquitouscomputing Development
      • 7.3.2 Basic forms of Ubiquitouscomputing
      • 7.3.3 Augmented Reality
      • 7.3.4 Mobilecomputing
    • 7.4 grid, Dist ributed andcloudcomputing
      • 7.4.1 characteristics ofgridcomputing
      • 7.4.2 the Advantages and Disadvantages of gridcomputing
      • 7.4.3 Distributedcomputing
      • 7.4.4 Distributed Systems
      • 7.4.5 Parallel and Distributedcomputing
      • 7.4.6 Distributedcomputing Architectures
      • 7.4.7 cloudcomputi ng
      • 7.4.8 technical Aspects of cloudcomputing
      • 7.4.9 Security Aspects of cloudcomputing
      • 7.4.10 Ongoing and Future Elements incloudcomputing
      • 7.4.11 Adoption ofcloudcomputing Industry Drivers
    • 7.5 Int ernetcomput ing
      • 7.5.1 Internetcomputingconcept and Model
      • 7.5.2 Benefit of Internetcomputing for Businesses
      • 7.5.3 Examples of Internetcomputing
      • 7.5.4 Migrating Internetcomputing
    • 7.6 Virtualization
      • 7.6.1 typesof Virtualization
      • 7.6.2 Hi story of Virtualiz ation
      • 7.6.3 Vi rtual izat ion Architecture
      • 7.6.4 Vi rtual Machine Monitor
      • 7.6.5 Examples of Virtual Machines
    • 7.7 Biocomputers
      • 7.7.1 Biochemicalcomputers
      • 7.7.2 Biomechanicalcomputers
      • 7.7.3 Bioelectroniccompute r s
    • 7.8 Summary
    • Exerci ses
    • References
  • 8 Assemblylanguage and Operating Systems
    • 8.1 Assemblylanguage Basics
      • 8.1.1 Numbering Systems
      • 8.1.2the Binary Numbering System and Baseconversions
      • 8.1.3the Hexadecimal Numbering System
      • 8.1.4 Signed and Unsigned Numbers
    • 8.2 Operationcode and Operands
    • 8.3 Di rect Addressing
    • 8.4 Indirect Addressing
    • 8.5 Stack and Buffer Overflow
      • 8.5.1calling Procedures UsingcALL and RET (Return)
      • 8.5.2 Exploiting Stack Buffer Overflows
      • 8.5.3 Stack Protection
    • 8.6 FIFO and M/M/1 Problem
      • 8.6.1 FIFO Data Structure
      • 8.6.2 M/M/1 Model
    • 8.7 Kernel, Drivers and OS Security
      • 8.7.1 Kernel
      • 8.7.2 BIOS
      • 8.7.3 Bootloader
      • 8.7.4 Device Drivers
    • 8.8 Summary
    • Exerci ses
    • References
  • 9 tCP/IP and Internet
    • 9.1 Datacommunications
      • 9.1.1 Signal, Data, andchannels
      • 9.1.2 Signal Encoding and Modulation
      • 9.1.3 Shannontheorem
    • 9.2 tCP/ IP Protocol
      • 9.2.1 Networktopology
      • 9.2.2 transmissioncontrol Protocol (TCP)
      • 9.2.3 the User Datagram Protocol (UDP)
      • 9.2.4 Internet Protocol (IP)
    • 9.3 Network Switches
      • 9.3.1 layer 1 Hubs
      • 9.3.2 Ethernet Switch
    • 9.4 Rout ers
      • 9.4.1 History of Routers
      • 9.4.2 Architecture
      • 9.4.3 Internet Protocol Version 4 (IPv4)
      • 9.4.4 Internet Protocol Version 6 (IPv6)
      • 9.4.5 Open Shortest Path First
      • 9.4.6throughput and Delay
    • 9.5 gateways
    • 9.6 Wireless Networks and Network Addresstranslation (NAT)
      • 9.6.1 Wireless Networks
      • 9.6.2 Wireless Protocols
      • 9.6.3 WLAN Handshaking, War Driving, and WLAN Security
      • 9.6.4 Security Measuresto Reduce Wireless Attacks
      • 9.6.5 the Future of Wireless Network
      • 9.6.6 Network Addresstranslation
      • 9.6.7 Environmental and Healthconcerns Usingcellular and Wireless Devices
    • 9.7 Network Security
      • 9.7.1 Introduction
      • 9.7.2 Firewall Architecture
      • 9.7.3constraint andlimitations of Firewall
      • 9.7.4 Enterprise Firewalls
    • 9.8 Summary
    • Exercises
    • 9.9 Virtualcyber-Securitylaboratory
    • References
  • 10 Design and Implementation: Modifying Neumann Architecture
    • 10.1 Data Security incomputer Systems
      • 10.1.1computer Security
      • 10.1.2 Data Security and Data Bleaches
      • 10.1.3 Researches in Architecture Security
    • 10.2 Single-Bus View of Neumann Architecture
      • 10.2.1 John von Neumanncomputer Architecture
      • 10.2.2 Modified Neumanncomputer Architecture
      • 10.2.3 Problems Exist in John Neumann Model
    • 10.3 A Dual-Bus Solut ion
    • 10.4 Buscont roller
      • 10.4.1 Working Mechanism ofthe Buscontroller
      • 10.4.2co-processor Board
    • 10.5 Dual-Port Storage
    • 10.6 Micro-Operating System
    • 10.7 Summary
    • Exercises
    • 10.8 Projects
    • References
  • Appendix A Digitallogic Simulators
    • A.1cEDARlogic Simulator
    • A.2logisim
    • A.3 Digitallogic Simulator v0.4
    • A.4logicly
  • Appendix B computer Securitytools
    • B.1 Wireshark (Ethereal)
    • B.2 Met asploit
    • B.3 Nessus
    • B.4 Ai rcrack
    • B.5 Snort
    • B.6 cain and Abel
    • B.7 BackTrack
    • B.8 Netcat
    • B.9tcpdump
    • B.10 Johnthe Ripper
  • Appendix c Patent Application: Intrusion-Freecomputer Architecture for Information and Data Security
    • C.1 Background of the Invention
      • C.1.1 John von Neumanncomputer Architecture Model
      • C.1.2 Modified Neumanncomputer Architecture
      • C.1.3 Problems Existed inthe John Neumann Model
      • C.1.4 thegoal ofthe Invention
    • C.2 Field of Invention
    • C.3 Detailed Description of the Invention
    • C.4 claim
  • Index

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